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Journal of Fudan University(Natural Science)
0427-7104
2006 Issue 1
FPGA Validation Based on Embryonic Arrays Fault-Tolerant System
RONG Hao-liang;YU Cheng-fang
..............page:127-130
MPSK Adaptive Modulation by Using Software Radio
YUAN Yan;SHEN Wei-wei;WANG Zong-xin;TANG Min
..............page:131-134
Sequential Equivalence Check Using Cuts
HUANG Wei;TANG Pu-shan
..............page:102-106
A Fast-lock 2.4 GHz Frequency-synthesizer Adaptable to Bluetooth
LIU Rui-jin;YANG Lian-xing
..............page:96-101
Design Optimization of DFT for Multiple Branches
YING Jun;LIU Xun;CHENG Jun-xia
..............page:92-95,101
Low Supply Bandgap Voltage Reference
MAO Jing-wen;CHEN Ting-qian;CHEN Cheng;REN Jun-yan;YANG Li
..............page:87-91
A Novel Carrier Recovery Loop for Efficient Phase Noise Suppression
LI Zheng;SHEN Bo
..............page:77-81,86
Adaptive Rate Control for H. 264 Video
KO Chang-suk;YU Li-li;ZHU Qian;SHAO Qian-ming
..............page:73-76
A Novel MAC Scheme for Optimizing Fairness on Downlink and Uplink in WLAN
FENG Hui;WANG Ting;HU Bo
..............page:67-72
The Modified CCK Demodulating Algorithms for 802. 11b
HE Jin-jin;CHEN Qi;YANG Lian-xing
..............page:63-66
A Take/Hold Circuit for High Speed & Resolution ADC
HUANG Fei-peng;HUANG Yu-mei;FANG Jie;HONG Zhi-liang
..............page:58-62
LSP Transcoding between AMR, G. 723.1 and G. 729A
YU Zhi-gang;HU Bo
..............page:54-57
A Novel Design for Multilevel Storage and Superb Reliability in Phase-Change Memory
HONG Yang;LIN Yin-yin;TANG Tin-gao;BOMY Chen
..............page:49-53,72
An Improved Arithmetic Coding-Decoding Method Based on Look-up
ZHANG Wen-ni;HUA Yun;HU Bo
..............page:45-48
Adaptive Filter Implemented by Quantized LMS Algorithm and Its Low Power Design
LIU Ai-lin;YE Fan;WU Xin-hua;REN Jun-yan
..............page:39-44
Enhanced O-tree Algorithm for Obstacled Floorplanning
WEN Yu-jie;TONG Jia-rong
..............page:34-38
Design of An Offset Voltage Compensation Ratio-Capacitance Bandgap Voltage Reference
HE Jing-lan;LI Qiang;HAN Yi-feng;MIN Hao
..............page:30-33
The Physical Design Solution for Million-Gate SoC Under VDSM
ZENG Hong;ZENG Xuan;MIN Hao
..............page:26-29
Implementation of the Gigabit Ethernet 1000 BASE-T Physical Coding Sublayer
XU Wei;YE Fan;ZHENG Guo-xiang;Ren Jun-yan
..............page:16-20
A Low Power Signal-Detector Design and Its Implementation for RFID Systems
HE Jing-lan;LI Qiang;HAN Yi-feng;MIN Hao
..............page:12-15,20
Auto-Generation of Universal Test Pattern for FPGA Logic Resources
OUYANG Yi-Rong;TONG Jia-Rong
..............page:6-11
A Low Complexity Reed-Solomon Decoder for DVB System
SU Jia-ning;TIAN Jun-hua;SHEN Bo;MIN Hao
..............page:1-5