Electronics and Packaging 2005 Issue 6 A Whole Chip ESD Protection Design Technology for Deep Sub micron CMOS IC

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Electronics and Packaging
1681-1070
2005 Issue 6

A Whole Chip ESD Protection Design Technology for Deep Sub micron CMOS IC
Zang Jia-feng;Xue Zhong-jie

..............page:26-30,7

A Modified Current-Sensing Technique for DC-DC Converters
SONG Li-jun;Wang Hu-gang

..............page:23-25

Limitations and Countermeasures of EMC in Packaging Molding
Xie Guang-chao

..............page:19-22

CSP Causes the Revolution of Memory Chip Package Technology
Xian Fei

..............page:16-18,15

Study on QFN wire bonding process based on NiPdAu PPF leadframe
Li Jian-guo;YANG Hong-bo;Zhu Bing

..............page:12-15

An Investigation into Temperature Field Simulation System of Micro-Electronics Metal Packaging
Tan Yan-hui;XU Ji-qian;XU Jun-yu;Chen Juan

..............page:8-11

ti sheng wo guo ban dao ti feng zhuang ye fa zhan de dong neng ji fang lue
yu zuo kang

..............page:1-7

A Survey of VLSI Power/Ground Network Design Methods
Yan Wen-fang;MA Qi

..............page:31-34

A Study of 0.8 μm PD SOI MOS Transistor
XIAO Zhi-qiang;Hong Gen-shen;Zhang Bo

..............page:35-39

Intelligence-control Switching Power Supplies
OU Gu-ping;Liu Wang-dong

..............page:40-42

intel zhong guo feng zhuang ji shu yan fa zhong xin cheng li zhuan jia chan shu xing ye xian zhuang yu qu shi
liu lin fa

..............page:43,42

xin xi bao dao

..............page:22,44,45,46,47