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Journal of Circuits and Systems
1007-0249
2000 Issue 4
BCH Decoding Using FPGA
SUN Yi;TIAN Shang-li;LIN Jian-ying
..............page:98-100
Design and Implementation of A Hybrid 4-in-1 Power Controller Chip
CHEN Lu;SHI Bing-xue;LU Chun
..............page:93-97
Continuous-Time Voltage-Mode CCH+/- Biquad Filter
PENG Liang-yu;HE Yi-gang;HUANG Man-chi
..............page:90-92
A CORBA-Based Network Management Architecture
QIU Xue-song;LI Wen-jing;MENG Luo-ming;CHEN Jun-liang
..............page:86-89
Representation and Realization of two-port Mutator
XIONG Yuan-xin
..............page:78-81
Improve the Quality of Zero-tree Encoded Images using Wiener Filtering
DENG Jin-quan;CAI Han-tian
..............page:70-72
From period-doubling to chaos in a new double scroll circuit containing a nonlinear capacitor
GAO Jin-feng;LI Guang-ming;WANG Jun-kun
..............page:66-69
Engineering Solutions to Fourier Coefficients
YANG Qi-wen;LIN Feng;JIANG Jing-ping
..............page:58-61
Optimal Design for the Variable Feedback Synchronization of Chua's Circuits
LU Yuan-yuan;HU Qing-bin;QIU Shui-sheng
..............page:53-57
Optimal Biorthogonal Analysis Window Functions for Real Gabor Transforms
TAO Liang;ZHANG De-long;KWAN H K
..............page:48-52
Realization of Calculator Circuit with Chaotic Method
TONG Qin-ye;JIN Min;YU Jie
..............page:33-37
Working Characteristics and Energy Dissipation Analysis of Adiabatic Switching
HANG Guo-qiang;WU Xun-wei
..............page:27-32
Feed-forward Neural Network Modeling for Noise Rejection
WANG Sou-jiao;LI Zhao-zhou;WANG Bo-nan;DING Hao-jiang
..............page:21-26
Third-order double sampled cascaded Sigma-delta modulator
BI Zhuo;SHI Yan
..............page:17-20
Design of Short Frame Turbo Code Interleaver with Low Resource Requirement
ZHANG Shen-ru;YE Yong-tao;WANG Ting-chang
..............page:12-16
MMSE Receiver with Space-time Coding for Downlink WCDMA Systems
WU Gang;CHENG Jian;CHENG Shi-xin
..............page:1-5